r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 58

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Caches
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Section 8 L Memory
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Section 9 Interrupt Controller (INTC)
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Table 9.8
Table 9.9
Section 10 SuperHyway Bus Bridge (SBR)
Table 10.1
Table 10.2
Section 11 Local Bus State Controller (LBSC)
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 11.7
Table 11.8
Table 11.9
Table 11.10
Table 11.11
Table 11.12
Table 11.13
Table 11.14
Rev. 1.00 Oct. 01, 2007 Page lviii of lxvi
Cache Features...................................................................................................... 187
Store Queue Features ............................................................................................ 187
Register Configuration.......................................................................................... 190
Register States in Each Processing State .............................................................. 190
L Memory Addresses............................................................................................ 217
Register Configuration.......................................................................................... 218
Register Status in Each Processing State .............................................................. 219
Protective Function Exceptions to Access L Memory.......................................... 231
Interrupt Types........................................................................................................ 82
INTC Pin Configuration ......................................................................................... 86
INTC Register Configuration ................................................................................. 87
Register States in Each Operating Mode ................................................................ 90
Interrupt Request Sources and INT2PRI0 to INT2PRI13..................................... 113
RL[3:0], IRL[7:4] Pins and Interrupt Levels ........................................................ 140
Interrupt Exception Handling and Priority............................................................ 143
Interrupt Response Time....................................................................................... 154
Switching Sequence of IRQ7/IRL7 to IRQ0/IRL0 Pin Function ......................... 156
Register Configuration.......................................................................................... 316
Register State in Each Operating Mode................................................................ 316
Pin Configuration.................................................................................................. 324
LBSC External Memory Space Map .................................................................... 327
Setting of bus width for area 0.............................................................................. 330
Correspondence between External Pin (MD5) and Endian .................................. 331
PCMCIA Interface Features ................................................................................. 331
PCMCIA Support Interface .................................................................................. 332
Register Configuration.......................................................................................... 335
Register State in Each Operating Made. ............................................................... 335
32-Bit External Device/Big-Endian Access and Data Alignment......................... 359
16-Bit External Device/Big-Endian Access and Data Alignment..................... 359
8-Bit External Device/Big-Endian Access and Data Alignment ...................... 360
32-Bit External Device/Little-Endian Access and Data Alignment.................. 361
16-Bit External Device/Little-Endian Access and Data Alignment.................. 361
8-Bit External Device/Little-Endian Access and Data Alignment.................... 362