r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 107

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

31
Notes: 1.
(a) Register configuration
in user mode
Figure 2.2 CPU Register Configuration in Each Processing Mode
2.
3.
4.
R0 _ BANK0*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
R0 is used as the index register in indexed register-indirect addressing mode and
indexed GBR indirect addressing mode.
Banked registers
Banked registers
Accessed as general registers when the RB bit is set to 1 in SR. Accessed only by
LDC/STC instructions when the RB bit is cleared to 0.
Banked registers
Accessed as general registers when the RB bit is cleared to 0 in SR. Accessed only
by LDC/STC instructions when the RB bit is set to 1.
MACH
MACL
GBR
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
1,
2
2
2
2
2
2
2
*
2
0
31
(b) Register configuration in
privileged mode (RB = 1)
R0 _ BANK1*
R0 _ BANK0*
R1 _ BANK1*
R2 _ BANK1*
R3 _ BANK1*
R4 _ BANK1*
R5 _ BANK1*
R6 _ BANK1*
R7 _ BANK1*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
MACH
MACL
GBR
SGR
SSR
VBR
SPC
DBR
R10
R11
R12
R13
R14
R15
PR
SR
PC
R8
R9
1,
1,
*
3
3
3
3
3
3
3
*
4
4
4
4
4
4
4
3
4
0
Rev. 1.00 Oct. 01, 2007 Page 41 of 1956
31
(c) Register configuration in
privileged mode (RB = 0)
Section 2 Programming Model
R0 _ BANK0*
R0 _ BANK1*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
R1 _ BANK1*
R2 _ BANK1*
R3 _ BANK1*
R4 _ BANK1*
R5 _ BANK1*
R6 _ BANK1*
R7 _ BANK1*
MACH
MACL
GBR
SGR
DBR
SSR
VBR
SPC
R10
R11
R12
R13
R14
R15
PR
R8
R9
SR
PC
1,
1,
*
4
4
4
4
4
4
4
*
3
3
3
3
3
3
3
REJ09B0256-0100
4
3
0