r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1183
r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
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Thus, the reception margin in asynchronous mode is given by formula (1).
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L:
F:
From equation (1), if F = 0 and D = 0.5, the reception margin is 46.875%, as given by formula (2).
When D = 0.5 and F = 0:
However, this is a theoretical value. A reasonable margin to allow in system designs is 20% to
30%.
(6)
When using an external clock as the synchronization clock, after SCFTDR is updated by the
DMAC, an external clock should be input after at least five peripheral clock (Pck) cycles. A
malfunction may occur when the transfer clock is input within four cycles after updating SCFTDR
(see figure 27.23).
Frame length (L = 9 to 12)
Absolute value of clock rate deviation
When Using the DMAC
M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ............................................... (2)
M= (0.5 -
Figure 27.23 Example of Synchronization Clock Transfer by DMAC
SCIF_CLK
TDRE
SCIF_TXD
Note: When the SCIF is operated on an external clock, set t > 4.
2N
1
) - (L - 0.5) F -
t
D0
D1
| D - 0.5 |
Section 27 Serial Communication Interface with FIFO (SCIF)
N
D2
(1 + F) × 100 % .................. (1)
D3
Rev. 1.00 Oct. 01, 2007 Page 1117 of 1956
D4
D5
D6
D7
REJ09B0256-0100
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