r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 40

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Figure 6.9 Flowchart of Memory Access Using UTLB.............................................................. 160
Figure 6.10 Flowchart of Memory Access Using ITLB ............................................................. 161
Figure 6.11 Operation of LDTLB Instruction............................................................................. 164
Figure 6.12 Memory-Mapped ITLB Address Array................................................................... 173
Figure 6.13 Memory-Mapped ITLB Data Array ........................................................................ 174
Figure 6.14 Memory-Mapped UTLB Address Array ................................................................. 176
Figure 6.15 Memory-Mapped UTLB Data Array....................................................................... 177
Figure 6.16 Physical Address Space (32-Bit Address Extended Mode)..................................... 177
Figure 6.17 PMB Configuration ................................................................................................. 179
Figure 6.18 Memory-Mapped PMB Address Array ................................................................... 183
Figure 6.19 Memory-Mapped PMB Data Array......................................................................... 183
Section 7 Caches
Figure 7.1 Configuration of Operand Cache (OC) ..................................................................... 188
Figure 7.2 Configuration of Instruction Cache (IC) ................................................................... 189
Figure 7.3 Configuration of Write-Back Buffer ......................................................................... 201
Figure 7.4 Configuration of Write-Through Buffer.................................................................... 201
Figure 7.5 Memory-Mapped IC Address Array ......................................................................... 207
Figure 7.6 Memory-Mapped IC Data Array ............................................................................... 208
Figure 7.7 Memory-Mapped OC Address Array........................................................................ 210
Figure 7.8 Memory-Mapped OC Data Array ............................................................................. 211
Figure 7.9 Store Queue Configuration........................................................................................ 212
Section 9 Interrupt Controller (INTC)
Figure 9.1 Block Diagram of INTC............................................................................................ 234
Figure 9.2 Example of IRL Interrupt Connection....................................................................... 293
Figure 9.3 On-chip Module Interrupt Priority ............................................................................ 296
Figure 9.4 Interrupt Operation Flowchart................................................................................... 306
Figure 9.5 Example of Interrupt Handling Routine .................................................................... 309
Section 10 SuperHyway Bus Bridge (SBR)
Figure 10.1 SBR Block Diagram................................................................................................ 313
Figure 10.2 Bus Arbitration by the SBR..................................................................................... 317
Section 11 Local Bus State Controller (LBSC)
Figure 11.1 LBSC Block Diagram ............................................................................................. 321
Figure 11.2 Correspondence between Virtual Address Space and External Memory Space...... 325
Figure 11.3 External Memory Space Allocation ........................................................................ 327
Figure 11.4 Basic Timing of SRAM Interface............................................................................ 366
Figure 11.5 Example of 32-Bit Data-Width SRAM Connection................................................ 367
Figure 11.6 Example of 16-Bit Data-Width SRAM Connection................................................ 368
Figure 11.7 Example of 8-Bit Data-Width SRAM Connection.................................................. 368
Rev. 1.00 Oct. 01, 2007 Page xl of lxvi