r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1743

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

39.4
The D/A converter incorporates two D/A channels that can operate individually.
The D/A converter executes D/A conversion while analog output is enabled by the D/A control
register (DACR). If the D/A data registers (DADR0 and DADR1) are modified, the D/A
converter immediately initiates the new data conversion. When the DAOE1 and DAOE0 bits in
the DACR register are set to 1, D/A conversion results are output.
An example of D/A conversion for channel 0 is shown below. The operation timing is shown in
figure 39.2.
1. Write conversion data to DADR0.
2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. The results are output after
3. When D/A data register 0 (DMDR0) is modified, the conversion starts again.
4. When the DAOE0 bit is cleared to 0, analog output is disabled (high-impedance state).
the conversion has ended. The output value will be (DADR0 contents/256) × AVcc.
The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is
cleared to 0.
The results are output after the conversion has ended.
Address bus
Operation
DADR0
DAOE0
[Legend]
t
Pck0
DCONV
DA0
: D/A conversion time
write cycle
DADR0
High impedance
state
Figure 39.2 D/A Converter Operation Example
write cycle
DACR
t
DCONV
Conversion data (1)
Conversion result (1)
Rev. 1.00 Oct. 01, 2007 Page 1677 of 1956
write cycle
DADR0
Section 39 D/A Converter (DAC)
t
DCONV
Conversion data (2)
Conversion
result (2)
write cycle
DACR
REJ09B0256-0100