r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1850

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 41 User Break Controller (UBC)

1. If the instruction fetch cycle is set in the match condition setting register (CBR0 or CBR1), the

2. If pre-instruction-execution break is specified for the instruction fetch cycle, the break is

3. If post-instruction-execution break is specified for the instruction fetch cycle, the break is

4. If the instruction fetch cycle is specified as the channel 1 match condition, the DBE bit of

Rev. 1.00 Oct. 01, 2007 Page 1784 of 1956

REJ09B0256-0100

instruction fetch cycle is handled as a match condition. To request a break upon satisfying the

match condition, set the BIE bit in the match operation setting register (CRR0 or CRR1) of the

corresponding channel. Either before or after executing the instruction can be selected as the

break timing according to the PCB bit value. If the instruction fetch cycle is specified as a

match condition, be sure to clear the LSB to 0 in the match address setting register (CAR0 or

CAR1); otherwise, no break occurs.

requested when the instruction is fetched and determined to be executed. Therefore, this

function cannot be used for the instructions which are fetched through overrun (i.e., the

instructions fetched during branching or making transition to the interrupt routine but not

executed). For priorities of pre-instruction-execution break and the other exceptions, refer to

section 5, Exception Handling. If pre-instruction-execution break is specified for the delayed

slot of the delayed branch instruction, the break is requested before the delayed branch

instruction is executed. However, do not specify pre-instruction-execution break for the

delayed slot of the RTE instruction.

requested after the instruction which satisfied the match condition has been executed and

before the next instruction is executed. Similar to pre-instruction-execution break, this

function cannot be used for the instructions which are fetched through overrun. For priorities

of post-instruction-execution break and the other exceptions, refer to section 5, Exception

Handling. If post-instruction-execution break is specified for the delayed branch instruction

and its delayed slot, the break does not occur until the first instruction at the branch

destination.

match condition setting register CBR1 becomes invalid, the settings of match data setting

value cannot be specified for the instruction fetch cycle break.

Instruction Fetch Cycle Break