r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1870

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 42 User Debugging Interface (H-UDI)
42.4.2
SDINT is a 16-bit register that can be read from or written to by the CPU. Specifying an H-UDI
interrupt command in SDIR via H-UDI pin (Update-IR) sets the INTREQ bit to 1. While an H-
UDI interrupt command is set in SDIR, SDINT which is connected between the TDI and TDO
pins can be read as a 32-bit register. In this case, the upper 16 bits will be 0 and the lower 16 bits
represent the SDINT value.
Only 0 can be written to the INTREQ bit by the CPU. While this bit is set to 1, an interrupt request
will continue to be generated. This bit, therefore, should be cleared by the interrupt handling
routine. It is initialized by TRST or in the Test-Logic-Reset state.
Rev. 1.00 Oct. 01, 2007 Page 1804 of 1956
REJ09B0256-0100
Initial value:
Bit
15 to 1
0
R/W:
Bit:
Interrupt Source Register (SDINT)
Bit Name

INTREQ
15
R
0
14
R
0
13
R
0
Initial
Value
All 0
0
12
R
0
11
R
0
R/W
R
R/W
10
R
0
Interrupt Request
Description
Reserved
For reading from or writing to this bit, see General
Precautions on Handling of Product.
Indicates whether or not an interrupt by an H-UDI
interrupt command has occurred. Clearing this bit to 0
by the CPU cancels an interrupt request. When writing
1 to this bit, the previous value is maintained.
R
9
0
R
8
0
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
INTREQ
R/W
0
0