LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 89
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 68.
Table 69.
Table 70.
UM10360
User manual
Bit
2:0
7:3
10:8
15:11 IP_CAN
18:16 Unimplemented
23:19 IP_DMA
26:24 Unimplemented
31:27 IP_I2S
Bit
2:0
7:3
10:8
15:11 IP_RIT
18:16 Unimplemented
23:19 IP_MCPWM
26:24 Unimplemented
31:27 IP_QEI
Bit
2:0
7:3
10:8
15:11 IP_USBACT
18:16 Unimplemented
23:19 IP_CANACT
31:24 Unimplemented
Name
Unimplemented
IP_USB
Unimplemented
Name
Unimplemented
IP_ENET
Unimplemented
Name
Unimplemented
IP_PLL1
Unimplemented
Interrupt Priority Register 6 (IPR6 - 0xE000 E418)
Interrupt Priority Register 7 (IPR7 - 0xE000 E41C)
Interrupt Priority Register 8 (IPR8 - 0xE000 E420)
6.5.17 Interrupt Priority Register 6 (IPR6 - 0xE000 E418)
6.5.18 Interrupt Priority Register 7 (IPR7 - 0xE000 E41C)
6.5.19 Interrupt Priority Register 8 (IPR8 - 0xE000 E420)
The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
The IPR7 register controls the priority of the eighth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
The IPR8 register controls the priority of the ninth and last group of 4 peripheral interrupts.
Each interrupt can have one of 32 priorities, where 0 is the highest priority.
Function
These bits ignore writes, and read as 0.
USB Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
CAN Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
GPDMA Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
I
Function
These bits ignore writes, and read as 0.
Ethernet Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
Repetitive Interrupt Timer Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
Motor Control PWM Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
Quadrature Encoder Interface Interrupt Priority. See functional description for bits 7-3.
Function
These bits ignore writes, and read as 0.
PLL1 (USB PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
USB Activity Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
CAN Activity Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
2
S Interrupt Priority. See functional description for bits 7-3.
All information provided in this document is subject to legal disclaimers.
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
Rev. 2 — 19 August 2010
UM10360
© NXP B.V. 2010. All rights reserved.
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