LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 576

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
29.5 Register description
Table 530. ADC registers
[1]
UM10360
User manual
Generic
Name
ADCR
ADGDR
ADINTEN
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADSTAT
ADTRM
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Description
A/D Control Register. The ADCR register must be written to select the
operating mode before A/D conversion can occur.
A/D Global Data Register. This register contains the ADC’s DONE bit and
the result of the most recent A/D conversion.
A/D Interrupt Enable Register. This register contains enable bits that allow
the DONE flag of each A/D channel to be included or excluded from
contributing to the generation of an A/D interrupt.
A/D Channel 0 Data Register. This register contains the result of the most
recent conversion completed on channel 0.
A/D Channel 1 Data Register. This register contains the result of the most
recent conversion completed on channel 1.
A/D Channel 2 Data Register. This register contains the result of the most
recent conversion completed on channel 2.
A/D Channel 3 Data Register. This register contains the result of the most
recent conversion completed on channel 3.
A/D Channel 4 Data Register. This register contains the result of the most
recent conversion completed on channel 4.
A/D Channel 5 Data Register. This register contains the result of the most
recent conversion completed on channel 5.
A/D Channel 6 Data Register. This register contains the result of the most
recent conversion completed on channel 6.
A/D Channel 7 Data Register. This register contains the result of the most
recent conversion completed on channel 7.
A/D Status Register. This register contains DONE and OVERRUN flags
for all of the A/D channels, as well as the A/D interrupt/DMA flag.
ADC trim register.
The A/D Converter registers are shown in
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
Table
530.
Access
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
value
1
NA
0x100
NA
NA
NA
NA
NA
NA
NA
NA
0
0x0000
0F00
UM10360
© NXP B.V. 2010. All rights reserved.
[1]
AD0 Name &
Address
AD0CR -
0x4003 4000
AD0GDR -
0x4003 4004
AD0INTEN -
0x4003 400C
AD0DR0 -
0x4003 4010
AD0DR1 -
0x4003 4014
AD0DR2 -
0x4003 4018
AD0DR3 -
0x4003 401C
AD0DR4 -
0x4003 4020
AD0DR5 -
0x4003 4024
AD0DR6 -
0x4003 4028
AD0DR7 -
0x4003 402C
AD0STAT -
0x4003 4030
AD0TRM -
0x4003 4034
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