LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 240

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 233. USB End of Transfer Interrupt Clear register (USBEoTIntClr - address 0x5000 C2A4) bit description
Table 234. USB End of Transfer Interrupt Set register (USBEoTIntSet - address 0x5000 C2A8) bit description
Table 235. USB New DD Request Interrupt Status register (USBNDDRIntSt - address 0x5000 C2AC) bit description
Table 236. USB New DD Request Interrupt Clear register (USBNDDRIntClr - address 0x5000 C2B0) bit description
UM10360
User manual
Bit
31:0
Bit
31:0
Bit
31:0
Bit
31:0
Symbol
EPxx
Symbol
EPxx
Symbol
EPxx
Symbol
EPxx
11.10.7.12 USB End of Transfer Interrupt Set register (USBEoTIntSet - 0x5000 C2A8)
11.10.7.13 USB New DD Request Interrupt Status register (USBNDDRIntSt - 0x5000
11.10.7.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0x5000
11.10.7.15 USB New DD Request Interrupt Set register (USBNDDRIntSet - 0x5000
Value
0
1
Value
0
1
Value
0
1
Value
0
1
Writing one to a bit in this register sets the corresponding bit in the USBEoTIntSt register.
Writing zero has no effect. USBEoTIntSet is a write-only register.
A bit in this register is set when a transfer is requested from the USB device and no valid
DD is detected for the corresponding endpoint. USBNDDRIntSt is a read-only register.
Writing one to a bit in this register clears the corresponding bit in the USBNDDRIntSt
register. Writing zero has no effect. USBNDDRIntClr is a write-only register.
Writing one to a bit in this register sets the corresponding bit in the USBNDDRIntSt
register. Writing zero has no effect. USBNDDRIntSet is a write-only register
C2AC)
C2B0)
C2B4)
Description
Clear endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request.
No effect.
Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
Description
Clear endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request.
No effect.
Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
Set endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request.
Description
No effect.
Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
Description
Endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request.
There is no new DD interrupt request for endpoint xx.
There is a new DD interrupt request for endpoint xx.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
0
Reset value
0
Reset value
0
Reset value
0
240 of 840