LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 310

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
14.4.10.2 Auto-baud modes
When the software is expecting an “AT” command, it configures the UARTn with the
expected character format and sets the UnACR Start bit. The initial values in the divisor
latches UnDLM and UnDLM don‘t care. Because of the “A” or “a” ASCII coding
(”A" = 0x41, “a” = 0x61), the UARTn Rx pin sensed start bit and the LSB of the expected
character are delimited by two falling edges. When the UnACR Start bit is set, the
auto-baud protocol will execute the following phases:
1. On UnACR Start bit setting, the baud rate measurement counter is reset and the
2. A falling edge on UARTn Rx pin triggers the beginning of the start bit. The rate
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
4. During the receipt of the start bit (and the character LSB for mode = 0) the rate
5. If Mode = 0 then the rate counter will stop on next falling edge of the UARTn Rx pin. If
6. The rate counter is loaded into UnDLM/UnDLL and the baud-rate will be switched to
ratemin
UARTn UnRSR is reset. The UnRSR baud rate is switch to the highest rate.
measuring counter will start counting pclk cycles optionally pre-scaled by the
fractional baud-rate generator.
the frequency of the (fractional baud-rate pre-scaled) UARTn input clock,
guaranteeing the start bit is stored in the UnRSR.
counter will continue incrementing with the pre-scaled UARTn input clock (pclk).
Mode = 1 then the rate counter will stop on the next rising edge of the UARTn Rx pin.
normal operation. After setting the UnDLM/UnDLL the end of auto-baud interrupt
UnIIR ABEOInt will be set, if enabled. The UnRSR will now continue receiving the
remaining bits of the “A/a” character.
=
2 P
------------------------ -
16 2 15
× CLK
All information provided in this document is subject to legal disclaimers.
×
Rev. 2 — 19 August 2010
≤
UART
n
baudrate
≤
----------------------------------------------------------------------------------------------------------- -
16
×
(
2
+
databits
Chapter 14: LPC17xx UART0/2/3
PCLK
+
paritybits
+
UM10360
stopbits
© NXP B.V. 2010. All rights reserved.
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