LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 442

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
19.8.2 I
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to “not addressed” slave receiver mode. The STO flag is
cleared by hardware automatically.
SI is the I
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in I2CONCLR register. The SI bit
should be cleared only after the required bit(s) has (have) been set and the value in I2DAT
has been loaded or read.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)
will be returned during the acknowledge clock pulse on the SCL line on the following
situations:
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA
is 0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge
clock pulse on the SCL line on the following situations:
0x4001 C018; I
0x400A 0018)
The I2CONCLR registers control clearing of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
I2CONCLR is a write-only register. The value of the related bits can be read from the
I2CONSET register.
Table 385. I
Bit
1:0
2
3
2
1. A matching address defined by registers I2ADR0 through I2ADR3, masked by
2. The General Call address has been received while the General Call bit (GC) in I2ADR
3. A data byte has been received while the I
4. A data byte has been received while the I
1. A data byte has been received while the I
2. A data byte has been received while the I
C Control Clear register (I2CONCLR: I
I2MASK0 though I2MASK3, has been received.
is set.
Symbol Description
-
AAC
SIC
2
C Interrupt Flag. This bit is set when the I
I2C1CONCLR - 0x4005 C018; I
2
C Control Clear register (I2CONCLR: I
All information provided in this document is subject to legal disclaimers.
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Assert acknowledge Clear bit.
I
2
2
C interrupt Clear bit.
C interface. Writing a one to a bit of this register causes the
2
C1, I2C1CONCLR - 0x4005 C018; I
Rev. 2 — 19 August 2010
2
C control register to be cleared. Writing a zero has no effect.
2
C2, I2C2CONCLR - 0x400A 0018) bit description
2
2
2
2
C is in the master receiver mode.
C is in the addressed slave receiver mode
C is in the master receiver mode.
C is in the addressed slave receiver mode.
2
C0, I2C0CONCLR - 0x4001 C018; I
2
C0, I2C0CONCLR -
2
C state changes. However, entering
Chapter 19: LPC17xx I2C0/1/2
2
C2, I2C2CONCLR -
UM10360
© NXP B.V. 2010. All rights reserved.
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2
C1,