LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 491

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
21.3 Applications
21.4 Description
21.5 Pin description
Table 424. Timer/Counter pin description
UM10360
User manual
Pin
CAP0[1:0]
CAP1[1:0]
CAP2[1:0]
CAP3[1:0]
MAT0[1:0]
MAT1[1:0]
MAT2[3:0]
MAT3[1:0]
Type
Input
Output
21.5.1 Multiple CAP and MAT pins
Description
Capture Signals- A transition on a capture pin can be configured to load one of the Capture Registers
with the value in the Timer Counter and optionally generate an interrupt. Capture functionality can be
selected from a number of pins. When more than one pin is selected for a Capture input on a single
TIMER0/1 channel, the pin with the lowest Port number is used
Timer/Counter block can select a capture signal as a clock source instead of the PCLK derived clock.
For more details see
External Match Output - When a match register (MR3:0) equals the timer counter (TC) this output can
either toggle, go low, go high, or do nothing. The External Match Register (EMR) controls the
functionality of this output. Match Output functionality can be selected on a number of pins in parallel.
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally-supplied clock, and can optionally generate interrupts or perform other actions
at specified timer values, based on four match registers. It also includes four capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
Table 424
Software can select from multiple pins for the CAP or MAT functions in the Pin Select
registers, which are described in
MAT output, all such pins are driven identically. When more than one pin is selected for a
CAP input, the pin with the lowest Port number is used. Note that match conditions may
be used internally without the use of a device pin.
•
•
•
Interval Timer for counting internal events.
Pulse Width Demodulator via Capture inputs.
Free running timer.
gives a brief summary of each of the Timer/Counter related pins.
All information provided in this document is subject to legal disclaimers.
Section
Rev. 2 — 19 August 2010
21.6.3.
Section
8.5. When more than one pin is selected for a
Chapter 21: LPC17xx Timer 0/1/2/3
UM10360
© NXP B.V. 2010. All rights reserved.
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