LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 550

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 484: QEI Control register (QEICON - address 0x400B C000) bit description
Table 485: QEI Configuration register (QEICONF - address 0x400B C008) bit description
Table 486: QEI Interrupt Status register (QEISTAT - address 0x400B C004) bit description
UM10360
User manual
Bit
0
1
2
3
31:4
Bit
0
1
2
3
31:4
Bit
0
31:1
Symbol
RESP
RESPI
RESV
RESI
-
Symbol
DIRINV
SIGMODE
CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB
INVINX
-
Symbol
DIR
-
26.6.2.1 QEI Control register (QEICON - 0x400B C000)
26.6.2.2 QEI Configuration register (QEICONF - 0x400B C008)
26.6.2.3 QEI Status register (QEISTAT - 0x400B C004)
26.6.2 Control registers
Description
Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when
the position counter is cleared.
Reset position counter on index. When set = 1, resets the position counter to all zeros when an
index pulse occurs. Autoclears when the position counter is cleared.
Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity
timer. Autoclears when the velocity counter is cleared.
Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the
index counter is cleared.
reserved
Description
Direction invert. When = 1, complements the DIR bit.
Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA
functions as the direction signal and PhB functions as the clock signal.
edges are counted (4X), increasing resolution but decreasing range.
Invert Index. When set, inverts the sense of the index input.
reserved
Description
Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See
Table
reserved
This register contains bits which control the operation of the position and velocity counters
of the QEI module.
This register contains the configuration of the QEI module.
This register provides the status of the encoder interface.
481.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 26: LPC17xx Quadrature Encoder Interface (QEI)
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
value
0
0
0
0
0
Reset
value
0
Reset
value
0
0
0
0
0