LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 590

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 542. Endian behavior
UM10360
User manual
Source
endian
Big
Big
Big
Big
Big
Big
Big
Big
31.4.1.6.3 Error conditions
Destination
endian
Big
Big
Big
Big
Big
Big
Big
Big
An error during a DMA transfer is flagged directly by the peripheral by asserting an Error
response on the AHB bus during the transfer. The DMA Controller automatically disables
the DMA stream after the current transfer has completed, and can optionally generate an
error interrupt to the CPU. This error interrupt can be masked.
Source
width
8
8
16
16
…continued
32
16
32
32
All information provided in this document is subject to legal disclaimers.
Destination
width
16
32
8
16
32
8
16
32
Rev. 2 — 19 August 2010
Source
transfer
no/byte lane
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
1/[31:24]
1/[23:16]
2/[15:8]
2/[7:0]
1/[31:24]
1/[23:16]
2/[15:8]
2/[7:0]
1/[31:24]
1/[23:16]
2/[15:8]
2/[7:0]
1/[31:24]
1/[23:16]
1/[15:8]
1/[7:0]
1/[31:24]
1/[23:16]
1/[15:8]
1/[7:0]
1/[31:24]
1/[23:16]
1/[15:8]
1/[7:0]
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
Source data Destination
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
transfer
no/byte lane
1/[15:0]
2/[31:16]
1/[31:0]
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
1/[15:0]
2/[31:16]
1/[31:0]
1/[31:24]
2/[23:16]
3/[15:8]
4/[7:0]
1/[15:0]
2/[31:16]
1/[31:0]
UM10360
© NXP B.V. 2010. All rights reserved.
Destination data
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56785678
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56565656
78787878
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56785678
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12121212
34343434
56565656
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