LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 649

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 612. Cortex-M3 instructions
UM10360
User manual
Mnemonic
SDIV
SEV
SMLAL
SMULL
SSAT
STM
STMDB, STMEA
STMFD, STMIA
STR
STRB, STRBT
STRD
STREX
STREXB
STREXH
STRH, STRHT
STRT
SUB, SUBS
SUB, SUBW
SVC
SXTB
SXTH
TBB
TBH
TEQ
TST
UBFX
UDIV
UMLAL
UMULL
USAT
UXTB
UXTH
WFE
WFI
Operands
{Rd,} Rn, Rm
-
RdLo, RdHi, Rn, Rm
RdLo, RdHi, Rn, Rm
Rd, #n, Rm {,shift #s} Signed Saturate
Rn{!}, reglist
Rn{!}, reglist
Rn{!}, reglist
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, Rt2, [Rn, #offset] Store Register two words
Rd, Rt, [Rn, #offset]
Rd, Rt, [Rn]
Rd, Rt, [Rn]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
{Rd,} Rn, Op2
{Rd,} Rn, #imm12
#imm
{Rd,} Rm {,ROR #n}
{Rd,} Rm {,ROR #n}
[Rn, Rm]
[Rn, Rm, LSL #1]
Rn, Op2
Rn, Op2
Rd, Rn, #lsb, #width
{Rd,} Rn, Rm
RdLo, RdHi, Rn, Rm
RdLo, RdHi, Rn, Rm
Rd, #n, Rm {,shift #s} Unsigned Saturate
{Rd,} Rm {,ROR #n}
{Rd,} Rm {,ROR #n}
-
-
…continued
All information provided in this document is subject to legal disclaimers.
Brief description
Signed Divide
Send Event
Signed Multiply with Accumulate (32 x 32 + 64),
64-bit result
Signed Multiply (32 x 32), 64-bit result
Store Multiple registers, increment after
Store Multiple registers, decrement before
Store Multiple registers, increment after
Store Register word
Store Register byte
Store Register Exclusive
Store Register Exclusive byte
Store Register Exclusive halfword
Store Register halfword
Store Register word
Subtract
Subtract
Supervisor Call
Sign extend a byte
Sign extend a halfword
Table Branch Byte
Table Branch Halfword
Test Equivalence
Test
Unsigned Bit Field Extract
Unsigned Divide
Unsigned Multiply with Accumulate
(32 x 32 + 64), 64-bit result
Unsigned Multiply (32 x 32), 64-bit result
Zero extend a byte
Zero extend a halfword
Wait For Event
Wait For Interrupt
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
Flags
-
-
-
-
Q
-
-
-
-
-
-
-
-
-
-
-
N,Z,C,V
N,Z,C,V
-
-
-
-
-
N,Z,C
N,Z,C
-
-
-
-
Q
-
-
-
-
UM10360
© NXP B.V. 2010. All rights reserved.
Page
Section 34.2.6.3
Section 34.2.10.9
Section 34.2.6.2
Section 34.2.6.2
Section 34.2.7.1
Section 34.2.4.6
Section 34.2.4.6
Section 34.2.4.6
Section 34.2.4
Section 34.2.4
Section 34.2.4.2
Section 34.2.4.8
Section 34.2.4.8
Section 34.2.4.8
Section 34.2.4
Section 34.2.4
Section 34.2.5.1
Section 34.2.5.1
Section 34.2.10.1
0
Section 34.2.8.3
Section 34.2.8.3
Section 34.2.9.4
Section 34.2.9.4
Section 34.2.5.9
Section 34.2.5.9
Section 34.2.8.2
Section 34.2.6.3
Section 34.2.6.2
Section 34.2.6.2
Section 34.2.7.1
Section 34.2.8.3
Section 34.2.8.3
Section 34.2.10.1
1
Section 34.2.10.1
2
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