LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 745

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.3.3.1 Exception states
34.3.3.2 Exception types
34.3.3 Exception model
This section describes the exception model.
Each exception is in one of the following states:
The exception types are:
•
•
•
•
•
•
•
•
Inactive
The exception is not active and not pending.
Pending
The exception is waiting to be serviced by the processor.
An interrupt request from a peripheral or from software can change the state of the
corresponding interrupt to pending.
Active
An exception that is being serviced by the processor but has not completed.
Remark: An exception handler can interrupt the execution of another exception
handler. In this case both exceptions are in the active state.
Active and pending
The exception is being serviced by the processor and there is a pending exception
from the same source.
Reset
Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor
stops, potentially at any point in an instruction. When reset is deasserted, execution
restarts from the address provided by the reset entry in the vector table. Execution
restarts as privileged execution in Thread mode.
NMI
A NonMaskable Interrupt (NMI) can be signalled by a peripheral or triggered by
software. This is the highest priority exception other than reset. It is permanently
enabled and has a fixed priority of -2. NMIs cannot be:
– masked or prevented from activation by any other exception
– preempted by any exception other than Reset.
Hard fault
A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception
mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority
than any exception with configurable priority.
Memory management fault
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
745 of 840