LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 776

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Table 667. SHCSR bit assignments
[1]
[2]
[3]
If you disable a system handler and the corresponding fault occurs, the processor treats
the fault as a hard fault.
You can write to this register to change the pending or active status of system exceptions.
An OS kernel can write to the active bits to perform a context switch that changes the
current exception type.
Caution
Bits
[31:19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6:4]
[3]
[2]
[1]
[0]
•
•
Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception.
Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. You can write to these bits to
change the pending status of the exceptions.
Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change
the active status of the exceptions, but see the Caution in this section.
Software that changes the value of an active bit in this register without correct
adjustment to the stacked content can cause the processor to generate a fault
exception. Ensure software that writes to this register retains and subsequently
restores the current active status.
After you have enabled the system handlers, if you have to change the value of a bit
in this register you must use a read-modify-write procedure to ensure that you change
only the required bit.
Name
-
USGFAULTENA
BUSFAULTENA
MEMFAULTENA
SVCALLPENDED
BUSFAULTPENDED
MEMFAULTPENDED Memory management fault exception pending bit, reads as 1 if
USGFAULTPENDED Usage fault exception pending bit, reads as 1 if exception is
SYSTICKACT
PENDSVACT
-
MONITORACT
SVCALLACT
-
USGFAULTACT
-
BUSFAULTACT
MEMFAULTACT
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Function
Reserved
Usage fault enable bit, set to 1 to enable
Bus fault enable bit, set to 1 to enable
Memory management fault enable bit, set to 1 to enable
SVC call pending bit, reads as 1 if exception is pending
Bus fault exception pending bit, reads as 1 if exception is
pending
exception is pending
pending
SysTick exception active bit, reads as 1 if exception is active
PendSV exception active bit, reads as 1 if exception is active
Reserved
Debug monitor active bit, reads as 1 if Debug monitor is active
SVC call active bit, reads as 1 if SVC call is active
Reserved
Usage fault exception active bit, reads as 1 if exception is
active
Reserved
Bus fault exception active bit, reads as 1 if exception is active
Memory management fault exception active bit, reads as 1 if
exception is active
[2]
[2]
Chapter 34: Appendix: Cortex-M3 user guide
[2]
[1]
[1]
UM10360
© NXP B.V. 2010. All rights reserved.
776 of 840
[2]
[1]
[3]