LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 531

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 469. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
Symbol
TC0MCI0_RE
TC0MCI0_FE
TC0MCI1_RE
TC0MCI1_FE
TC0MCI2_RE
TC0MCI2_FE
TC1MCI0_RE
TC1MCI0_FE
TC1MCI1_RE
TC1MCI1_FE
TC1MCI2_RE
TC1MCI2_FE
TC2MCI0_RE
25.7.4.1 MCPWM Count Control read address (MCCNTCON - 0x400B 805C)
25.7.4 MCPWM Count Control register
Table 468. MCPWM Interrupt Flags clear address (PWMINTF_CLR - 0x400B 8070) bit
The MCCNTCON register controls whether the MCPWM channels are in timer or counter
mode, and in counter mode whether the counter advances on rising and/or falling edges
on any or all of the three MCI inputs. If timer mode is selected, the counter advances
based on the PCLK clock.
This address is read-only. To set or clear the register bits, write ones to the
MCCNTCON_SET or MCCNTCON_CLR address.
Value Description
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit
31:0
Description
register, thus clearing the corresponding interrupt request(s). See
Writing one(s) to this write-only address sets the corresponding bit(s) in the MCINTF
If MODE0 is 1, counter 0 advances on a rising edge on MCI0.
A rising edge on MCI0 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a falling edge on MCI0.
A falling edge on MCI0 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a rising edge on MCI1.
A rising edge on MCI1 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a falling edge on MCI1.
A falling edge on MCI1 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a rising edge on MCI2.
A rising edge on MCI0 does not affect counter 0.
If MODE0 is 1, counter 0 advances on a falling edge on MCI2.
A falling edge on MCI0 does not affect counter 0.
If MODE1 is 1, counter 1 advances on a rising edge on MCI0.
A rising edge on MCI0 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a falling edge on MCI0.
A falling edge on MCI0 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a rising edge on MCI1.
A rising edge on MCI1 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a falling edge on MCI1.
A falling edge on MCI0 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a rising edge on MCI2.
A rising edge on MCI2 does not affect counter 1.
If MODE1 is 1, counter 1 advances on a falling edge on MCI2.
A falling edge on MCI2 does not affect counter 1.
If MODE2 is 1, counter 2 advances on a rising edge on MCI0.
A rising edge on MCI0 does not affect counter 2.
description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 25: LPC17xx Motor control PWM
Table
UM10360
© NXP B.V. 2010. All rights reserved.
462.
531 of 840
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Value