LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 667

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.4.4.1 Syntax
34.2.4.4.2 Operation
34.2.4.4.3 Restrictions
34.2.4.4.4 Condition flags
34.2.4.4 LDR and STR, unprivileged
Load and Store with unprivileged access.
op{type}T{cond} Rt, [Rn {, #offset}]
where:
op is one of:
type is one of:
cond is an optional condition code, see
Rt is the register to load or store.
Rn is the register on which the memory address is based.
offset is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value
in Rn.
These load and store instructions perform the same function as the memory access
instructions with immediate offset, see
instructions have only unprivileged access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way
as normal memory access instructions with immediate offset.
In these instructions:
These instructions do not change the flags.
•
•
LDR: Load Register.
STR: Store Register.
B: unsigned byte, zero extend to 32 bits on loads.
SB: signed byte, sign extend to 32 bits (LDR only).
H: unsigned halfword, zero extend to 32 bits on loads.
SH: signed halfword, sign extend to 32 bits (LDR only).
—: omit, for word.
Rn must not be PC
Rt must not be SP and must not be PC.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
; immediate offset
Section
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
34.2.4.2. The difference is that these
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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