LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 580

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 535: A/D Status register (AD0STAT - address 0x4003 4030) bit description
Table 536: A/D Trim register (ADTRM - address 0x4003 4034) bit description
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
31:17 -
Bit
3:0
7:4
11:8
31:12 -
Symbol
-
ADCOFFS
TRIM
Symbol
DONE0
DONE1
DONE2
DONE3
DONE4
DONE5
DONE6
DONE7
OVERRUN0
OVERRUN1
OVERRUN2
OVERRUN3
OVERRUN4
OVERRUN5
OVERRUN6
OVERRUN7
ADINT
29.5.5 A/D Status register (ADSTAT - 0x4003 4030)
29.5.6 A/D Trim register (ADTRIM - 0x4003 4034)
Description
reserved.
Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user. 0
written-to by boot code. Can not be overwritten by the user. These bits are locked after boot
code write.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel
are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found
in ADSTAT.
Description
This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0.
This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1.
This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2.
This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4.
This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5.
This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6.
This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7.
This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done
flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
This register will be set by the bootcode on start-up. It contains the trim values for the DAC
and the ADC. The offset trim values for the ADC can be overwritten by the user. All 12 bits
are visible when this register is read.
This bit mirrors the DONE status flag from the result register for A/D channel 0.
This bit mirrors the DONE status flag from the result register for A/D channel 1.
This bit mirrors the DONE status flag from the result register for A/D channel 2.
This bit mirrors the DONE status flag from the result register for A/D channel 3.
This bit mirrors the DONE status flag from the result register for A/D channel 4.
This bit mirrors the DONE status flag from the result register for A/D channel 5.
This bit mirrors the DONE status flag from the result register for A/D channel 6.
This bit mirrors the DONE status flag from the result register for A/D channel 7.
This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
UM10360
© NXP B.V. 2010. All rights reserved.
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0
0
0
0
0
0
0
0
Reset
value
0
0
0
0
0
0
0
0
0
NA
Reset
value
NA
1111
NA