LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 562
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 508. Interrupt Location Register (ILR - address 0x4002 4000) bit description
Table 509. Clock Control Register (CCR - address 0x4002 4008) bit description
UM10360
User manual
Bit
0
1
31:21 -
Bit
0
Symbol
RTCCIF
RTCALF
Symbol
CLKEN
27.6.2.1 Interrupt Location Register (ILR - 0x4002 4000)
27.6.2.2 Clock Control Register (CCR - 0x4002 4008)
27.6.1 RTC interrupts
27.6.2 Miscellaneous register group
Description
When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit
location clears the counter increment interrupt.
When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the
alarm interrupt.
Reserved, user software should not write ones to reserved bits. The value read from a reserved
bit is not defined.
Value Description
1
0
Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter
Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register
(AMR). Interrupts are generated only by the transition into the interrupt state. The ILR
separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of the
time counters. If CIIR is enabled for a particular counter, then every time the counter is
incremented an interrupt is generated. The alarm registers allow the user to specify a date
and time for an interrupt to be generated. The AMR provides a mechanism to mask alarm
compares. If all non-masked alarm registers match the value in their corresponding time
counter, then an interrupt is generated.
The RTC interrupt can bring the microcontroller out of Power-down mode when the RTC
is operating from its own oscillator on the RTCX1-2 pins. When the RTC interrupt is
enabled for wake-up and its selected event occurs, the oscillator wake-up cycle
associated with the XTAL1/2 pins is started. For details on the RTC based wake-up
process see
Section 4.9 “Wake-up timer” on page
The Interrupt Location Register is a 2-bit register that specifies which blocks are
generating an interrupt (see
corresponding interrupt. Writing a zero has no effect. This allows the programmer to read
this register and write back the same value to clear only the interrupt that is detected by
the read.
The clock register is a 4-bit register that controls the operation of the clock divide circuit.
Each bit of the clock register is described in
be initialized when the RTC is first turned on.
Clock Enable.
The time counters are enabled.
The time counters are disabled so that they may be initialized.
Section 4.8.8 “Wake-up from Reduced Power Modes” on page 62
All information provided in this document is subject to legal disclaimers.
Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers
Rev. 2 — 19 August 2010
Table
508). Writing a one to the appropriate bit clears the
65.
Table
509. All NC bits in this register should
UM10360
© NXP B.V. 2010. All rights reserved.
and
562 of 840
Reset
value
0
0
NA
Reset
value
NC
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