LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 518

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description
Table 450: PWM Capture Control Register (PWM1CCR - address 0x4001 8028) bit description
UM10360
User manual
Bit
14
15
16
17
18
19
20
31:21 -
Bit
0
1
2
Symbol
Capture on
CAPn.0 rising
edge
Capture on
CAPn.0 falling
edge
Interrupt on
CAPn.0 event
Symbol
PWMMR4S
PWMMR5I
PWMMR5R
PWMMR5S
PWMMR6I
PWMMR6R
PWMMR6S
24.6.5 PWM Capture Control Register (PWM1CCR - 0x4001 8028)
Value Description
1
0
1
0
1
0
1
0
1
0
1
0
1
Value Description
0
1
0
1
0
1
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when a capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
descriptions below, “n” represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR4 matches the PWMTC.
This feature is disabled
Interrupt on PWMMR5: An interrupt is generated when PWMMR5 matches the value
in the PWMTC.
This interrupt is disabled.
Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it.
This feature is disabled.
set to 0 if PWMMR5 matches the PWMTC.
This feature is disabled
Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in
the PWMTC.
This interrupt is disabled.
Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it.
This feature is disabled.
Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR6 matches the PWMTC.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
This feature is disabled.
A synchronously sampled rising edge on the CAPn.0 input will cause CR0 to be
loaded with the contents of the TC.
This feature is disabled.
A synchronously sampled falling edge on CAPn.0 will cause CR0 to be loaded with
the contents of TC.
This feature is disabled.
A CR0 load due to a CAPn.0 event will generate an interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
UM10360
© NXP B.V. 2010. All rights reserved.
518 of 840
Reset
Value
0
0
0
Reset
Value
0
0
0
0
0
0
0
NA