LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 594

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 544. GPDMA register map
[1]
UM10360
User manual
Name
DMACC2Config
Channel 3 registers
DMACC3SrcAddr
DMACC3DestAddr
DMACC3LLI
DMACC3Control
DMACC3Config
Channel 4 registers
DMACC4SrcAddr
DMACC4DestAddr
DMACC4LLI
DMACC4Control
DMACC4Config
Channel 5 registers
DMACC5SrcAddr
DMACC5DestAddr
DMACC5LLI
DMACC5Control
DMACC5Config
Channel 6 registers
DMACC6SrcAddr
DMACC6DestAddr
DMACC6LLI
DMACC6Control
DMACC6Config
Channel 7 registers
DMACC7SrcAddr
DMACC7DestAddr
DMACC7LLI
DMACC7Control
DMACC7Config
Bit 17 of this register is a read-only status flag.
Description
DMA Channel 2 Configuration Register
DMA Channel 3 Source Address Register
DMA Channel 3 Destination Address Register
DMA Channel 3 Linked List Item Register
DMA Channel 3 Control Register
DMA Channel 3 Configuration Register
DMA Channel 4 Source Address Register
DMA Channel 4 Destination Address Register
DMA Channel 4 Linked List Item Register
DMA Channel 4 Control Register
DMA Channel 4 Configuration Register
DMA Channel 5 Source Address Register
DMA Channel 5 Destination Address Register
DMA Channel 5 Linked List Item Register
DMA Channel 5 Control Register
DMA Channel 5 Configuration Register
DMA Channel 6 Source Address Register
DMA Channel 6 Destination Address Register
DMA Channel 6 Linked List Item Register
DMA Channel 6 Control Register
DMA Channel 6 Configuration Register
DMA Channel 7 Source Address Register
DMA Channel 7 Destination Address Register
DMA Channel 7 Linked List Item Register
DMA Channel 7 Control Register
DMA Channel 7 Configuration Register
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
R/W
R/W
Access Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
state
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[1]
[1]
[1]
[1]
[1]
[1]
UM10360
© NXP B.V. 2010. All rights reserved.
0x5000 4160
0x5000 4168
0x5000 416C
0x5000 4180
0x5000 4188
0x5000 418C
0x5000 41A0
0x5000 41A8
0x5000 41AC
0x5000 41C0
0x5000 41C4
0x5000 41C8
0x5000 41CC
0x5000 41E0
0x5000 41E8
0x5000 41EC
Address
0x5000 4150
0x5000 4164
0x5000 4170
0x5000 4184
0x5000 4190
0x5000 41A4
0x5000 41B0
0x5000 41D0
0x5000 41E4
0x5000 41F0
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