LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 773

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.3.8 Configuration and Control Register
Table 661. SCR bit assignments
The CCR controls entry to Thread mode and enables:
See the register summary in
The bit assignments are shown in
Bits
[31:5]
[4]
[3]
[2]
[1]
[0]
•
•
•
the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore bus
faults
trapping of divide by zero and unaligned accesses
access to the STIR by unprivileged software, see
Name
-
SEVONPEND
-
SLEEPDEEP
SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Function
Reserved.
Send Event on Pending bit:
0 = only enabled interrupts or events can wakeup the processor,
disabled interrupts are excluded
1 = enabled events and all interrupts, including disabled interrupts,
can wakeup the processor.
When an event or interrupt enters pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting
for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction or
an external event.
Reserved.
Controls whether the processor uses sleep or deep sleep as its low
power mode:
0 = sleep
1 = deep sleep.
Thread mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt driven application to avoid
returning to an empty main application.
Reserved.
Table 654
Table
for the CCR attributes.
662.
Chapter 34: Appendix: Cortex-M3 user guide
Table
652.
UM10360
© NXP B.V. 2010. All rights reserved.
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