LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 247

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 245. Set Device Status command bit description
UM10360
User manual
Bit
0
1
2
3
Symbol
CON
CON_CH
SUS
SUS_CH
11.12.5 Read Test Register (Command: 0xFD, Data: read 2 bytes)
11.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte)
Value
0
1
0
1
0
1
0
1
The test register is 16 bits wide. It returns the value of 0xA50F if the USB clocks (usbclk
and AHB slave clock) are running.
The Set Device Status command sets bits in the Device Status Register.
•
•
Description
The Connect bit indicates the current connect status of the device. It controls the
CONNECT output pin, used for SoftConnect. Reading the connect bit returns the
current connect status. This bit is cleared by hardware when the V
input is LOW for more than 3 ms. The 3 ms delay filters out temporary dips in the
V
Writing a 0 will make the CONNECT pin go HIGH.
Writing a 1 will make the CONNECT pin go LOW.
Connect Change.
This bit is cleared when read.
This bit is set when the device’s pull-up resistor is disconnected because V
disappeared. The DEV_STAT interrupt is generated when this bit is 1.
Suspend: The Suspend bit represents the current suspend state.
When the device is suspended (SUS = 1) and the CPU writes a 0 into it, the
device will generate a remote wake-up. This will only happen when the device is
connected (CON = 1). When the device is not connected or not suspended,
writing a 0 has no effect. Writing a 1 to this bit has no effect.
This bit is reset to 0 on any activity.
This bit is set to 1 when the device hasn’t seen any activity on its upstream port
for more than 3 ms.
Suspend (SUS) bit change indicator. The SUS bit can toggle because:
This bit is cleared when read.
SUS bit not changed.
SUS bit changed. At the same time a DEV_STAT interrupt is generated.
In case no SOF was received by the device at the beginning of a frame, the frame
number returned is that of the last successfully received SOF.
In case the SOF frame number contained a CRC error, the frame number returned will
be the corrupted frame number as received by the device.
BUS
•
•
•
The device goes into the suspended state.
The device is disconnected.
The device receives resume signalling on its upstream port.
voltage.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
BUS
status
UM10360
© NXP B.V. 2010. All rights reserved.
BUS
0
Reset value
0
0
0
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