LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 542

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
25.8.8 Interrupts
The MCPWM includes 10 possible interrupt sources:
Section 25.7.3 “MCPWM Interrupt registers”
Section 25.7.2 “MCPWM Capture Control register”
MCI0-2 inputs to “capture events” on the three channels.
Fig 127. Three-phase AC mode sample waveforms, edge aligned PWM mode
•
•
•
•
When any channel’s TC matches its Match register.
When any channel’s TC matches its Limit register.
When any channel captures the value of its TC into its Capture register, because a
selected edge occurs on any of MCI0-2.
When all three channels’ outputs are forced to “A passive” state because the
MCABORT pin goes low.
MCOB2
MCOA2
MCOB1
MCOA1
MCOB0
MCOA0
All information provided in this document is subject to legal disclaimers.
0
MAT1
Rev. 2 — 19 August 2010
MAT0
MAT2
timer reset
LIM0
MAT1
explains how to enable these interrupts, and
Chapter 25: LPC17xx Motor control PWM
MAT2
describes how to map edges on the
timer reset
LIM0
UM10360
© NXP B.V. 2010. All rights reserved.
POLA2 = 0
POLA1 = 0
POLA0 = 0
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