LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 158

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
10.12 Control register definitions
UM10360
User manual
10.12.1 Command Register (Command - 0x5000 0100)
10.12.2 Status Register (Status - 0x5000 0104)
The station address is used for perfect address filtering and for sending pause control
frames. For the ordering of the octets in the packet please refer to
The Command register (Command) register has an address of 0x5000 0100. Its bit
definition is shown in
Table 148. Command register (Command - address 0x5000 0100) bit description
All bits can be written and read. The Tx/RxReset bits are write-only, reading will return a 0.
The Status register (Status) is a read-only register with an address of 0x5000 0104. Its bit
definition is shown in
Table 149. Status register (Status - address 0x5000 0104) bit description
The values represent the status of the two channels/data paths. When the status is 1, the
channel is active, meaning:
Bit
0
1
2
3
4
5
6
7
8
9
10
31:11
Bit
0
1
31:2
Symbol
RxStatus If 1, the receive channel is active. If 0, the receive channel is inactive.
TxStatus If 1, the transmit channel is active. If 0, the transmit channel is inactive. 0
-
Symbol
RxEnable
TxEnable
-
RegReset
TxReset
RxReset
PassRuntFrame
PassRxFilter
TxFlowControl
RMII
FullDuplex
-
All information provided in this document is subject to legal disclaimers.
Function
Unused
Table
Table
Rev. 2 — 19 August 2010
Function
Enable receive.
Enable transmit.
Unused
When a ’1’ is written, all datapaths and the host registers are
reset. The MAC needs to be reset separately.
When a ’1’ is written, the receive datapath is reset.
When set to ’1’, passes runt frames smaller than 64 bytes to
memory unless they have a CRC error. If ’0’ runt frames are
filtered out.
When set to ’1’, disables receive filtering i.e. all frames
received are written to memory.
Enable IEEE 802.3 / clause 31 flow control sending pause
frames in full duplex and continuous preamble in half duplex.
one during Ethernet initialization. See
When set to “1”, indicates full duplex operation.
Unused
When a ’1’ is written, the transmit datapath is reset.
When set to “1”, RMII mode is selected. This bit must be set to
148.
149.
Chapter 10: LPC17xx Ethernet
Section
Figure
10.17.2.
UM10360
© NXP B.V. 2010. All rights reserved.
18.
158 of 840
Reset
value
0
0
0x0
0
0
0
0
0
0
0
0
0x0
0
Reset
value
0x0