LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 646

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.1.1.3 Cortex-M3 processor features and benefits summary
34.1.1.4 Cortex-M3 core peripherals
LPC17xx devices support JTAG and Serial Wire Debug, Serial Wire Viewer, and include
the Embedded Trace Macrocell. See
These are:
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tight integration of system peripherals reduces area and development costs
Thumb instruction set combines high code density with 32-bit performance
code-patch ability for ROM system updates
power control optimization of system components
integrated sleep modes for low power consumption
fast code execution permits slower processor clock or increases sleep mode time
hardware division and fast multiplier
deterministic, high-performance interrupt handling for time-critical applications
optional memory protection unit (MPU) for safety-critical applications
extensive debug and trace capabilities:
– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for
Nested Vectored Interrupt Controller
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt
controller that supports low latency interrupt processing.
System control block
The System control block (SCB) is the programmers model interface to the
processor. It provides system implementation information and system control,
including configuration, control, and reporting of system exceptions.
System timer
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time
Operating System (RTOS) tick timer or as a simple counter.
Memory protection unit
The Memory protection unit (MPU) improves system reliability by defining the
memory attributes for different memory regions. It provides up to eight different
regions, and an optional predefined background region.
debugging and tracing.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 33.1
Chapter 34: Appendix: Cortex-M3 user guide
for additional information.
UM10360
© NXP B.V. 2010. All rights reserved.
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