LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 448

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 394. Example I
UM10360
User manual
(Fast Mode)
1 MHz (Fast
Mode Plus)
(Standard)
I
100 kHz
400 kHz
2
C
Rate
19.8.11 Selecting the appropriate I
60
15
6
-
2
C clock rates
Software must set values for the registers I2SCLH and I2SCLL to select the appropriate
data rate and duty cycle. I2SCLH defines the number of PCLK_I2C cycles for the SCL
HIGH time, I2SCLL defines the number of PCLK_I2C cycles for the SCL low time. The
frequency is determined by the following formula (PCLK_I2C is the frequency of the
peripheral bus APB):
The values for I2SCLL and I2SCLH must ensure that the data rate is in the appropriate
I
gives some examples of I
I2SCLH values.
I2SCLL and I2SCLH values should not necessarily be the same. Software can set
different duty cycles on SCL by setting these two registers. For example, the I
specification defines the SCL low time and high time at different values for a Fast Mode
and Fast Mode Plus I
80
20
2
8
8
C data rate range. Each register value must be greater than or equal to 4.
100
10
25
10
120
12
30
12
All information provided in this document is subject to legal disclaimers.
I2SCLL + I2SCLH values at PCLK_I2C (MHz)
160
2
16
40
16
C.
Rev. 2 — 19 August 2010
I 2 C
2
C-bus rates based on PCLK_I2C frequency and I2SCLL and
200
20
50
20
bitfrequency
2
300
C data rate and duty cycle
30
75
30
=
400
100
-------------------------------------------------------- -
I2CSCLH
40
40
PCLKI2C
500
125
50
50
+
I2CSCLL
600
150
60
60
Chapter 19: LPC17xx I2C0/1/2
700
175
70
70
UM10360
800
200
80
80
© NXP B.V. 2010. All rights reserved.
Table 394
900
225
90
90
2
C-bus
448 of 840
1000
250
100
100
(11)