LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 149

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 128. Ethernet register definitions
UM10360
User manual
Name
Status
RxDescriptor
RxStatus
RxDescriptorNumber
RxProduceIndex
RxConsumeIndex
TxDescriptor
TxStatus
TxDescriptorNumber
TxProduceIndex
TxConsumeIndex
TSV0
TSV1
RSV
FlowControlCounter
FlowControlStatus
Rx filter registers
RxFliterCtrl
RxFilterWoLStatus
RxFilterWoLClear
HashFilterL
HashFilterH
Module control registers
IntStatus
IntEnable
IntClear
IntSet
PowerDown
The third column in the table lists the accessibility of the register: read-only, write-only,
read/write.
All AHB register write transactions except for accesses to the interrupt registers are
posted i.e. the AHB transaction will complete before write data is actually committed to the
register. Accesses to the interrupt registers will only be completed by accepting the write
data when the data has been committed to the register.
Description
Status register.
Receive descriptor base address register.
Receive status base address register.
Receive number of descriptors register.
Receive produce index register.
Receive consume index register.
Transmit descriptor base address register.
Transmit status base address register.
Transmit number of descriptors register.
Transmit produce index register.
Transmit consume index register.
Transmit status vector 0 register.
Transmit status vector 1 register.
Receive status vector register.
Flow control counter register.
Flow control status register.
Receive filter control register.
Receive filter WoL status register.
Receive filter WoL clear register.
Hash filter table LSBs register.
Hash filter table MSBs register.
Interrupt status register.
Interrupt enable register.
Interrupt clear register.
Interrupt set register.
Power-down register.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
R/W
RO
R/W
Access
RO
R/W
WO
WO
Chapter 10: LPC17xx Ethernet
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
UM10360
© NXP B.V. 2010. All rights reserved.
0x5000 0108
0x5000 0110
0x5000 0124
Address
0x5000 0104
0x5000 010C
0x5000 0114
0x5000 0118
0x5000 011C
0x5000 0120
0x5000 0128
0x5000 012C
0x5000 0158
0x5000 015C
0x5000 0160
0x5000 0170
0x5000 0174
0x5000 0200
0x5000 0204
0x5000 0208
0x5000 0210
0x5000 0214
0x5000 0FE0
0x5000 0FE4
0x5000 0FE8
0x5000 0FEC
0x5000 0FF4
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