LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 408

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
17.7.2 SPI Status Register (S0SPSR - 0x4002 0004)
17.7.3 SPI Data Register (S0SPDR - 0x4002 0008)
17.7.4 SPI Clock Counter Register (S0SPCCR - 0x4002 000C)
The S0SPSR register controls the operation of SPI0 as per the configuration bits setting
shown in
Table 362: SPI Status Register (S0SPSR - address 0x4002 0004) bit description
This bi-directional data register provides the transmit and receive data for the SPI.
Transmit data is provided to the SPI by writing to this register. Data received by the SPI
can be read from this register. When used as a master, a write to this register will start an
SPI data transfer. Writes to this register will be blocked when a data transfer starts, or
when the SPIF status bit is set, and the SPI Status Register has not been read.
Table 363: SPI Data Register (S0SPDR - address 0x4002 0008) bit description
This register controls the frequency of a master’s SCK. The register indicates the number
of SPI peripheral clock cycles that make up an SPI clock.
Bit
2:0
3
4
5
6
7
31:8
Bit
7:0
15:8
31:16 -
Symbol
-
ABRT
MODF
ROVR
WCOL
SPIF
-
Symbol
DataLow
DataHigh
Table
362.
All information provided in this document is subject to legal disclaimers.
Description
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
This bit is cleared by reading this register.
Mode fault. when 1, this bit indicates that a Mode fault error has
occurred. This bit is cleared by reading this register, then writing the
SPI0 control register.
Read overrun. When 1, this bit indicates that a read overrun has
occurred. This bit is cleared by reading this register.
Write collision. When 1, this bit indicates that a write collision has
occurred. This bit is cleared by reading this register, then accessing the
SPI Data Register.
SPI transfer complete flag. When 1, this bit indicates when a SPI data
transfer is complete. When a master, this bit is set at the end of the last
cycle of the transfer. When a slave, this bit is set on the last data
sampling edge of the SCK. This bit is cleared by first reading this
register, then accessing the SPI Data Register.
Note: this is not the SPI interrupt flag. This flag is found in the SPINT
register.
value read from a reserved bit is not defined.
Slave abort. When 1, this bit indicates that a slave abort has occurred.
Reserved, user software should not write ones to reserved bits. The
Description
SPI Bi-directional data port.
If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all
of these bits contain the additional transmit and receive bits. When less
than 16 bits are selected, the more significant among these bits read
as zeroes.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 2 — 19 August 2010
Chapter 17: LPC17xx SPI
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
Value
NA
0
0
0
0
0
NA
Reset
Value
0x00
0x00
NA