LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 759

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
34.4 ARM Cortex-M3 User Guide: Peripherals
UM10360
User manual
34.4.1 About the Cortex-M3 peripherals
The address map of the Private peripheral bus (PPB) is:
Table 643. Core peripheral register regions
In register descriptions:
Address
0xE000E008 - 0xE000E00F
0xE000E010 - 0xE000E01F
0xE000E100 - 0xE000E4EF
0xE000ED00 - 0xE000ED3F
0xE000ED90 - 0xE000EDB8
0xE000EF00 - 0xE000EF03
•
•
the register type is described as follows:
– RW: Read and write.
– RO: Read-only.
– WO: Write-only.
the required privilege gives the privilege level required to access the register, as
follows:
– Privileged: Only privileged software can access the register
– Unprivileged: Both unprivileged and privileged software can access the register.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Core peripheral
System control block
System timer
Nested Vectored Interrupt
Controller
System control block
Memory Protection Unit
Nested Vectored Interrupt
Controller
Chapter 34: Appendix: Cortex-M3 user guide
Description
Table 654 “Summary of the
system control block registers”
Table 674 “System timer registers
summary”
Table 644 “NVIC register
summary”
Table 654 “Summary of the
system control block registers”
Table 680 “MPU registers
summary”
Table 644 “NVIC register
summary”
UM10360
© NXP B.V. 2010. All rights reserved.
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