LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 143

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
10.4 Architecture and operation
UM10360
User manual
Fig 17. Ethernet block diagram
interface (AHB
DMA interface
(AHB master)
register
slave)
Figure 17
The block diagram for the Ethernet block consists of:
•
•
•
•
•
ETHERNET
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision backoff and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
Physical interface:
– Attachment of external PHY chip through a standard Reduced MII (RMII) interface.
– PHY register access is available via the Media Independent Interface Management
The host registers module containing the registers in the software view and handling
AHB accesses to the Ethernet block. The host registers connect to the transmit and
receive data path as well as the MAC.
The DMA to AHB interface. This provides an AHB master connection that allows the
Ethernet block to access on-chip SRAM for reading of descriptors, writing of status,
and reading and writing data buffers.
The Ethernet MAC, which interfaces to the off-chip PHY via an RMII interface.
The transmit data path, including:
BLOCK
receive filters or a magic frame detection filter.
(MIIM) interface.
shows the internal architecture of the Ethernet block.
All information provided in this document is subject to legal disclaimers.
REGISTERS
TRANSMIT
RECEIVE
HOST
DMA
DMA
Rev. 2 — 19 August 2010
TRANSMIT
TRANSMIT
CONTROL
RECEIVE
RECEIVE
BUFFER
RETRY
FILTER
FLOW
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
RMII
MIIM
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