LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 77

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 52.
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
ISE_WDT
ISE_TIMER0
ISE_TIMER1
ISE_TIMER2
ISE_TIMER3
ISE_UART0
ISE_UART1
ISE_UART2
ISE_UART3
ISE_PWM
ISE_I2C0
ISE_I2C1
ISE_I2C2
ISE_SPI
ISE_SSP0
ISE_SSP1
ISE_PLL0
ISE_RTC
ISE_EINT0
ISE_EINT1
ISE_EINT2
ISE_EINT3
ISE_ADC
ISE_BOD
ISE_USB
ISE_CAN
ISE_DMA
ISE_I2S
ISE_ENET
ISE_RIT
ISE_MCPWM
ISE_QEI
Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100)
6.5.1 Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100)
Function
Watchdog Timer Interrupt Enable.
Write: writing 0 has no effect, writing 1 enables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Timer 0 Interrupt Enable. See functional description for bit 0.
Timer 1. Interrupt Enable. See functional description for bit 0.
Timer 2 Interrupt Enable. See functional description for bit 0.
Timer 3 Interrupt Enable. See functional description for bit 0.
UART0 Interrupt Enable. See functional description for bit 0.
UART1 Interrupt Enable. See functional description for bit 0.
UART2 Interrupt Enable. See functional description for bit 0.
UART3 Interrupt Enable. See functional description for bit 0.
PWM1 Interrupt Enable. See functional description for bit 0.
I
I
I
SPI Interrupt Enable. See functional description for bit 0.
SSP0 Interrupt Enable. See functional description for bit 0.
SSP1 Interrupt Enable. See functional description for bit 0.
PLL0 (Main PLL) Interrupt Enable. See functional description for bit 0.
Real Time Clock (RTC) Interrupt Enable. See functional description for bit 0.
External Interrupt 0 Interrupt Enable. See functional description for bit 0.
External Interrupt 1 Interrupt Enable. See functional description for bit 0.
External Interrupt 2 Interrupt Enable. See functional description for bit 0.
External Interrupt 3 Interrupt Enable. See functional description for bit 0.
ADC Interrupt Enable. See functional description for bit 0.
BOD Interrupt Enable. See functional description for bit 0.
USB Interrupt Enable. See functional description for bit 0.
CAN Interrupt Enable. See functional description for bit 0.
GPDMA Interrupt Enable. See functional description for bit 0.
I
Ethernet Interrupt Enable. See functional description for bit 0.
Repetitive Interrupt Timer Interrupt Enable. See functional description for bit 0.
Motor Control PWM Interrupt Enable. See functional description for bit 0.
Quadrature Encoder Interface Interrupt Enable. See functional description for bit 0.
The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. The remaining interrupts are enabled via the ISER1
register
registers
2
2
2
2
C0 Interrupt Enable. See functional description for bit 0.
C1 Interrupt Enable. See functional description for bit 0.
C2 Interrupt Enable. See functional description for bit 0.
S Interrupt Enable. See functional description for bit 0.
(Section
(Section 6.5.3
All information provided in this document is subject to legal disclaimers.
6.5.2). Disabling interrupts is done through the ICER0 and ICER1
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
Rev. 2 — 19 August 2010
and
Section
6.5.4).
UM10360
© NXP B.V. 2010. All rights reserved.
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