LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 608

IC ARM CORTEX MCU 512K 100-LQFP

LPC1767FBD100,551

Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr

Specifications of LPC1767FBD100,551

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-4967
935289808551

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1767FBD100,551
Quantity:
9 999
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
UM10360
User manual
31.6.1.6 Halting a DMA channel
31.6.1.7 Programming a DMA channel
31.6.2 Flow control
Set the halt bit in the relevant DMA channel configuration register. The current source
request is serviced. Any further source DMA request is ignored until the halt bit is cleared.
The device that controls the length of the packet is known as the flow controller. On the
LPC17xx, the flow controller is always the DMA Controller, and the packet length is
programmed by software before the DMA channel is enabled.
When the DMA transfer is completed:
The following sections describe the DMA Controller data flow sequences for the four
allowed transfer types:
Table 566
1. Read the DMACEnbldChns controller register and find out which channels are
2. Choose an inactive channel that has the required priority.
3. Program the DMA controller
1. Choose a free DMA channel with the priority needed. DMA channel 0 has the highest
2. Clear any pending interrupts on the channel to be used by writing to the
3. Write the source address into the DMACCxSrcAddr register.
4. Write the destination address into the DMACCxDestAddr register.
5. Write the address of the next LLI into the DMACCxLLI register. If the transfer
6. Write the control information into the DMACCxControl register.
7. Write the channel configuration information into the DMACCxConfig register. If the
1. The DMA Controller issues an acknowledge to the peripheral in order to indicate that
2. A TC interrupt is generated, if enabled.
3. The DMA Controller moves on to the next LLI.
inactive.
priority and DMA channel 7 the lowest priority.
DMACIntTCClear and DMACIntErrClear register. The previous channel operation
might have left interrupt active.
comprises of a single packet of data then 0 must be written into this register.
enable bit is set then the DMA channel is automatically enabled.
the transfer has finished.
Memory-to-peripheral.
Peripheral-to-memory.
Memory-to-memory.
Peripheral-to-peripheral.
indicates the request signals used for each type of transfer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
UM10360
© NXP B.V. 2010. All rights reserved.
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