LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 271

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 253. USB Host port pins
Table 254. USB Host register address definitions
UM10360
User manual
Pin name
USB_D+
USB_D −
USB_UP_LED
USB_PPWR
USB_PWRD
USB_OVRCR
Name
HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
HcPeriodCurrentED
12.4.1.1 USB host usage note
12.4.2.1 Register map
12.4.1 Pin description
12.4.2 Software interface
Direction
I/O
I/O
O
O
I
I
The USB block can be configured as USB host. For details on how to connect the USB
port, see the USB OTG chapter,
The USB device/host/OTG controller is disabled after RESET and must be enabled by
writing a 1 to the PCUSB bit in the PCONP register, see
The software interface of the USB host block consists of a register view and the format
definitions for the endpoint descriptors. For details on these two aspects see the OHCI
specification. The register map is shown in the next subsection.
The following registers are located in the AHB clock ‘cclk’ domain. They can be accessed
directly by the processor. All registers are 32 bits wide and aligned in the word address
boundaries.
Address
0x5000 C000
0x5000 C004
0x5000 C008
0x5000 C00C
0x5000 C010
0x5000 C014
0x5000 C018
0x5000 C01C
Description
Positive differential data
Negative differential data
GoodLink LED control signal
Port power enable
Port power status
Over-current status
All information provided in this document is subject to legal disclaimers.
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
[1]
Rev. 2 — 19 August 2010
Function
BCD representation of the version of the HCI
specification that is implemented by the Host Controller.
Defines the operating modes of the HC.
This register is used to receive the commands from the
Host Controller Driver (HCD). It also indicates the status
of the HC.
Indicates the status on various events that cause
hardware interrupts by setting the appropriate bits.
Controls the bits in the HcInterruptStatus register and
indicates which events will generate a hardware
interrupt.
The bits in this register are used to disable
corresponding bits in the HCInterruptStatus register and
in turn disable that event leading to hardware interrupt.
Contains the physical address of the host controller
communication area.
Contains the physical address of the current isochronous
or interrupt endpoint descriptor.
Section
13.7.
Chapter 12: LPC17xx USB Host controller
Table
Control
Host power switch
Type
USB Connector
USB Connector
Host power switch
Host power switch
46.
UM10360
© NXP B.V. 2010. All rights reserved.
0x0
Reset value
0x10
0x0
0x0
0x0
0x0
0x0
0x0
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