LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 421

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
18.6 Register description
[1]
UM10360
User manual
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
18.6.1 SSPn Control Register 0 (SSP0CR0 - 0x4008 8000, SSP1CR0 - 0x4003
The register addresses of the SSP controllers addresses are shown in
Table 369. SSP Register Map
0000)
This register controls the basic operation of the SSP controller.
Generic
Name
CR0
CR1
DR
SR
CPSR
IMSC
RIS
MIS
ICR
DMACR
Description
Control Register 0. Selects the
serial clock rate, bus type, and data
size.
Control Register 1. Selects
master/slave and other modes.
Data Register. Writes fill the
transmit FIFO, and reads empty
the receive FIFO.
Status Register
Clock Prescale Register
Interrupt Mask Set and Clear
Register
Raw Interrupt Status Register
Masked Interrupt Status Register
SSPICR Interrupt Clear Register
DMA Control Register
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Access
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Value
0
0
0
0
0
0
NA
0
[1]
Chapter 18: LPC17xx SSP0/1
SSPn Register
Name & Address
SSP0CR0 - 0x4008 8000
SSP1CR0 - 0x4003 0000
SSP0CR1 - 0x4008 8004
SSP1CR1 - 0x4003 0004
SSP0DR - 0x4008 8008
SSP1DR - 0x4003 0008
SSP0SR - 0x4008 800C
SSP1SR - 0x4003 000C
SSP0CPSR - 0x4008 8010
SSP1CPSR - 0x4003 0010
SSP0IMSC - 0x4008 8014
SSP1IMSC - 0x4003 0014
SSP0RIS - 0x4008 8018
SSP1RIS - 0x4003 0018
SSP0MIS - 0x4008 801C
SSP1MIS - 0x4003 001C
SSP0ICR - 0x4008 8020
SSP1ICR - 0x4003 0020
SSP0DMACR - 0x4008 8024
SSP1DMACR - 0x4003 0024
UM10360
Table
© NXP B.V. 2010. All rights reserved.
369.
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