LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 81

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 56.
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
ISP_WDT
ISP_TIMER0
ISP_TIMER1
ISP_TIMER2
ISP_TIMER3
ISP_UART0
ISP_UART1
ISP_UART2
ISP_UART3
ISP_PWM
ISP_I2C0
ISP_I2C1
ISP_I2C2
ISP_SPI
ISP_SSP0
ISP_SSP1
ISP_PLL0
ISP_RTC
ISP_EINT0
ISP_EINT1
ISP_EINT2
ISP_EINT3
ISP_ADC
ISP_BOD
ISP_USB
ISP_CAN
ISP_DMA
ISP_I2S
ISP_ENET
ISP_RIT
ISP_MCPWM
ISP_QEI
Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200)
6.5.5 Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200)
Function
Watchdog Timer Interrupt Pending set.
Write: writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
Timer 0 Interrupt Pending set. See functional description for bit 0.
Timer 1. Interrupt Pending set. See functional description for bit 0.
Timer 2 Interrupt Pending set. See functional description for bit 0.
Timer 3 Interrupt Pending set. See functional description for bit 0.
UART0 Interrupt Pending set. See functional description for bit 0.
UART1 Interrupt Pending set. See functional description for bit 0.
UART2 Interrupt Pending set. See functional description for bit 0.
UART3 Interrupt Pending set. See functional description for bit 0.
PWM1 Interrupt Pending set. See functional description for bit 0.
I
I
I
SPI Interrupt Pending set. See functional description for bit 0.
SSP0 Interrupt Pending set. See functional description for bit 0.
SSP1 Interrupt Pending set. See functional description for bit 0.
PLL0 (Main PLL) Interrupt Pending set. See functional description for bit 0.
Real Time Clock (RTC) Interrupt Pending set. See functional description for bit 0.
External Interrupt 0 Interrupt Pending set. See functional description for bit 0.
External Interrupt 1 Interrupt Pending set. See functional description for bit 0.
External Interrupt 2 Interrupt Pending set. See functional description for bit 0.
External Interrupt 3 Interrupt Pending set. See functional description for bit 0.
ADC Interrupt Pending set. See functional description for bit 0.
BOD Interrupt Pending set. See functional description for bit 0.
USB Interrupt Pending set. See functional description for bit 0.
CAN Interrupt Pending set. See functional description for bit 0.
GPDMA Interrupt Pending set. See functional description for bit 0.
I
Ethernet Interrupt Pending set. See functional description for bit 0.
Repetitive Interrupt Timer Interrupt Pending set. See functional description for bit 0.
Motor Control PWM Interrupt Pending set. See functional description for bit 0.
Quadrature Encoder Interface Interrupt Pending set. See functional description for bit 0.
The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or
for reading the pending state of those interrupts. The remaining interrupts can have their
pending state set via the ISPR1 register
interrupts is done through the ICPR0 and ICPR1 registers
Section
2
2
2
2
C0 Interrupt Pending set. See functional description for bit 0.
C1 Interrupt Pending set. See functional description for bit 0.
C2 Interrupt Pending set. See functional description for bit 0.
S Interrupt Pending set. See functional description for bit 0.
6.5.8).
All information provided in this document is subject to legal disclaimers.
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
Rev. 2 — 19 August 2010
(Section
6.5.6). Clearing the pending state of
(Section 6.5.7
UM10360
© NXP B.V. 2010. All rights reserved.
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