LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 789

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.5.3 MPU Region Number Register
34.4.5.4 MPU Region Base Address Register
XN and Strongly-ordered rules always apply to the System Control Space regardless of
the value of the ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled
for the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit
is set to 1 and no regions are enabled, then only privileged software can operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the
same memory attributes as if the MPU is not implemented, see
access
unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are
always permitted. Other areas are accessible based on regions and whether
PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing
the handler for an exception with priority –1 or –2. These priorities are only possible when
handling a hard fault or NMI exception, or when FAULTMASK is enabled. Setting the
HFNMIENA bit to 1 enables the MPU when operating with these two priorities.
The RNR selects which memory region is referenced by the RBAR and RASR registers.
See the register summary in
Table
Table 683. RNR bit assignments
Normally, you write the required region number to this register before accessing the
RBAR or RASR. However you can change the region number by writing to the RBAR with
the VALID bit set to 1, see
The RBAR defines the base address of the MPU region selected by the RNR, and can
update the value of the RNR. See the register summary in
Write RBAR with the VALID bit set to 1 to change the current region number and update
the RNR. The bit assignments are shown in
Bits
[31:8]
[7:0]
•
•
For privileged accesses, the default memory map is as described in
“Memory
memory region behaves as defined by the default memory map.
Any access by unprivileged software that does not address an enabled memory
region causes a memory management fault.
683.
behavior”. The default memory map applies to accesses from both privileged and
Name
-
REGION
model”. Any access by privileged software that does not address an enabled
All information provided in this document is subject to legal disclaimers.
Function
Reserved.
Indicates the MPU region referenced by the RBAR and RASR registers.
The MPU supports 8 memory regions, so the permitted values of this field
are 0-7.
Rev. 2 — 19 August 2010
Table
Table 680
684. This write updates the value of the REGION field.
for its attributes. The bit assignments are shown in
Chapter 34: Appendix: Cortex-M3 user guide
Table
684.
Table 680
Table 635 “Memory
for its attributes.
UM10360
© NXP B.V. 2010. All rights reserved.
Section 34.3.2
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