LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 496
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 429. Match Control Register (T[0/1/2/3]MCR - addresses 0x4000 4014, 0x4000 8014, 0x4009 0014, 0x4009 4014)
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
31:12 -
Symbol Value Description
MR0I
MR0R
MR0S
MR1I
MR1R
MR1S
MR2I
MR2R
MR2S
MR3I
MR3R
MR3S
bit description
21.6.7 Match Registers (MR0 - MR3)
21.6.8 Match Control Register (T[0/1/2/3]MCR - 0x4000 4014, 0x4000 8014,
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
0x4009 0014, 0x4009 4014)
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
This interrupt is disabled
Reset on MR0: the TC will be reset if MR0 matches it.
Feature disabled.
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
Feature disabled.
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
This interrupt is disabled
Reset on MR1: the TC will be reset if MR1 matches it.
Feature disabled.
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC.
Feature disabled.
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
This interrupt is disabled
Reset on MR2: the TC will be reset if MR2 matches it.
Feature disabled.
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC.
Feature disabled.
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
This interrupt is disabled
Reset on MR3: the TC will be reset if MR3 matches it.
Feature disabled.
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC.
Feature disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table
429.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 21: LPC17xx Timer 0/1/2/3
UM10360
© NXP B.V. 2010. All rights reserved.
496 of 840
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
NA
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