LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 520
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 451: PWM Control Register (PWM1PCR - address 0x4001 804C) bit description
Table 452: PWM Latch Enable Register (PWM1LER - address 0x4001 8050) bit description
UM10360
User manual
Bit
14
31:15 Unused
Bit
0
1
2
3
Symbol
Enable PWM
Match 0 Latch
Enable PWM
Match 1 Latch
Enable PWM
Match 2 Latch
Enable PWM
Match 3 Latch
Symbol
PWMENA6
24.6.7 PWM Latch Enable Register (PWM1LER - 0x4001 8050)
Value Description
1
0
The PWM Latch Enable Registers are used to control the update of the PWM Match
registers when they are used for PWM generation. When software writes to the location of
a PWM Match register while the Timer is in PWM mode, the value is captured, but not
used immediately.
When a PWM Match 0 event occurs (normally also resetting the timer in PWM mode), the
contents of shadow registers will be transferred to the shadow registers if the
corresponding bit in the Latch Enable Register has been set. At that point, the new values
will take effect and determine the course of the next PWM cycle. Once the transfer of new
values has taken place, all bits of the LER are automatically cleared. Until the
corresponding bit in the PWMLER is set and a PWM Match 0 event occurs, any value
written to the PWM Match registers has no effect on PWM operation.
For example, if PWM2 is configured for double edge operation and is currently running, a
typical sequence of events for changing the timing would be:
The order of writing the two PWM Match registers is not important, since neither value will
be used until after the write to LER. This insures that both values go into effect at the
same time, if that is required. A single value may be altered in the same way if needed.
The function of each of the bits in the LER is shown in
Description
Writing a one to this bit allows the last value written to the PWM Match 0 register to be
become effective when the timer is next reset by a PWM Match event. See
“PWM Match Control Register (PWM1MCR - 0x4001
Writing a one to this bit allows the last value written to the PWM Match 1 register to be
become effective when the timer is next reset by a PWM Match event. See
“PWM Match Control Register (PWM1MCR - 0x4001
Writing a one to this bit allows the last value written to the PWM Match 2 register to be
become effective when the timer is next reset by a PWM Match event. See
“PWM Match Control Register (PWM1MCR - 0x4001
Writing a one to this bit allows the last value written to the PWM Match 3 register to be
become effective when the timer is next reset by a PWM Match event. See
“PWM Match Control Register (PWM1MCR - 0x4001
•
•
•
•
The PWM6 output enabled.
The PWM6 output disabled.
Unused, always zero.
Write a new value to the PWM Match1 register.
Write a new value to the PWM Match2 register.
Write to the PWMLER, setting bits 1 and 2 at the same time.
The altered values will become effective at the next reset of the timer (when a PWM
Match 0 event occurs).
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
8014)”.
8014)”.
8014)”.
8014)”.
Table
452.
Section 24.6.4
Section 24.6.4
Section 24.6.4
Section 24.6.4
UM10360
© NXP B.V. 2010. All rights reserved.
520 of 840
Reset
Value
0
NA
Reset
Value
0
0
0
0
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