LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 280

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
13.8.7 OTG Timer Register (OTGTmr - 0x5000 C114)
13.8.8 OTG Clock Control Register (OTGClkCtrl - 0x5000 CFF4)
Table 259. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit description
Table 260. OTG Timer register (OTGTmr - address 0x5000 C114) bit description
This register controls the clocking of the OTG controller. Whenever software wants to
access the registers, the corresponding clock control bit needs to be set. The software
does not have to repeat this exercise for every register access, provided that the
corresponding OTGClkCtrl bits are already set.
Table 261. OTG clock control register (OTG_clock_control - address 0x5000 CFF4) bit
Bit
10
15:11 -
31:16 TMR_CNT
Bit
15:0
31:16 -
Bit
0
1
2
3
Symbol
PU_REMOVED
Symbol
TIMEOUT_CNT The TMR interrupt is set when TMR_CNT reaches this value.
Symbol
HOST_CLK_EN
DEV_CLK_EN
I2C_CLK_EN
OTG_CLK_EN
description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
When the B-device changes its role from peripheral to
host, software sets this bit when it removes the D+
pull-up, see
HNP_SUCCESS or HNP_FAILURE is set.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Current timer count value.
Value Description
0
1
0
1
0
1
0
1
Host clock enable
Disable the Host clock.
Enable the Host clock.
Device clock enable
Disable the Device clock.
Enable the Device clock.
I
Disable the I
Enable the I
OTG clock enable
Disable the OTG clock.
Enable the OTG clock.
2
C clock enable
Section
13.9. Hardware clears this bit when
2
2
C clock.
C clock.
Chapter 13: LPC17xx USB OTG
UM10360
© NXP B.V. 2010. All rights reserved.
Reset
Value
0xFFFF
NA
280 of 840
Reset
Value
0
0
0
0
Reset
Value
0
NA
0x0