LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 335

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 305: UART1 Fractional Divider Register (U1FDR - address 0x4001 0028) bit description
UM10360
User manual
Bit
3:0
7:4
31:8
Function
DIVADDVAL 0
MULVAL
-
15.4.16.1 Baud rate calculation
Value Description
1
NA
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART1 disabled making sure that UART1
is fully software and hardware compatible with UARTs not equipped with this feature.
UART1 baud rate can be calculated as (n = 1):
Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud
rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
The value of the U1FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
If the U1FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
UART1 can operate with or without using the Fractional Divider. In real-life applications it
is likely that the desired baud rate can be achieved using several different Fractional
Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a
relative error of less than 1.1% from the desired one.
1. 1 ≤ MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 14
3. DIVADDVAL < MULVAL
Baud-rate generation pre-scaler divisor value. If this field is 0, fractional
baud-rate generator will not impact the UARTn baudrate.
Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for
UARTn to operate properly, regardless of whether the fractional baud-rate
generator is used or not.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
UART1
All information provided in this document is subject to legal disclaimers.
baudrate
Rev. 2 — 19 August 2010
=
----------------------------------------------------------------------------------------------------------------------------------
16
×
(
256
×
U1DLM
+
PCLK
U1DLL
)
Chapter 15: LPC17xx UART1
×
⎛
⎝
1
+
DivAddVal
---------------------------- -
MulVal
UM10360
© NXP B.V. 2010. All rights reserved.
⎞
⎠
Reset value
0
1
0
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(4)