LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 204

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Fig 26. Transmit Active/Inactive state machine
10.17.14 Transmission padding and CRC
TxProduceIndex <> TxConsumeIndex
TxEnable = 1
After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set
in the Command register and the Produce and Consume indices are not equal, the state
machine transitions to the ACTIVE state. As soon as the TxEnable bit is cleared and the
transmit data path has completed all pending transmissions, including committing the
transmission status to memory, the state machine returns to the INACTIVE state. The
state machine will also return to the INACTIVE state if the Produce and Consume indices
are equal again i.e. all frames have been transmitted.
For the state machine in
a soft reset the transmit data path is inactive until the data path is re-enabled.
In the case of a frame of less than 60 bytes (or 64 bytes for VLAN frames), the Ethernet
block can pad the frame to 64 or 68 bytes including a 4 bytes CRC Frame Check
Sequence (FCS). Padding is affected by the value of the ‘AUTO DETECT PAD ENABLE’
(ADPEN), ‘VLAN PAD ENABLE’ (VLPEN) and ‘PAD/CRC ENABLE’ (PADEN) bits of the
MAC2 configuration register, as well as the Override and Pad bits from the transmit
descriptor Control word. CRC generation is affected by the ‘CRC ENABLE’ (CRCE) and
‘DELAYED CRC’ (DCRC) bits of the MAC2 configuration register, and the Override and
CRC bits from the transmit descriptor Control word.
The effective pad enable (EPADEN) is equal to the ‘PAD/CRC ENABLE’ bit from the
MAC2 register if the Override bit in the descriptor is 0. If the Override bit is 1, then
EPADEN will be taken from the descriptor Pad bit. Likewise the effective CRC enable
(ECRCE) equals CRCE if the Override bit is 0, otherwise it equal the CRC bit from the
descriptor.
If padding is required and enabled, a CRC will always be appended to the padded frames.
A CRC will only be appended to the non-padded frames if ECRCE is set.
If EPADEN is 0, the frame will not be padded and no CRC will be added unless ECRCE is
set.
AND
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Figure
TxStatus = 1
TxStatus = 0
INACTIVE
ACTIVE
26, a soft reset is like a hardware reset assertion, i.e. after
TxEnable = 0 and not busy transmitting
TxProduceIndex = TxConsumeIndex
reset
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Chapter 10: LPC17xx Ethernet
OR
UM10360
© NXP B.V. 2010. All rights reserved.
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