LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 749

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.3.3.6 Interrupt priority grouping
34.3.3.7 Exception entry and return
Remark: Configurable priority values are in the range 0 to 31. This means that the Reset,
Hard fault, and NMI exceptions, with fixed negative priority values, always have higher
priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to
IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are
asserted, IRQ[1] is processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the
lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are
pending and have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is
preempted if a higher priority exception occurs. If an exception occurs with the same
priority as the exception being handled, the handler is not preempted, irrespective of the
exception number. However, the status of the new interrupt changes to pending.
To increase priority control in systems with interrupts, the NVIC supports priority grouping.
This divides each interrupt priority register entry into two fields:
Only the group priority determines preemption of interrupt exceptions. When the
processor is executing an interrupt exception handler, another interrupt with the same
group priority as the interrupt being handled does not preempt the handler,
If multiple pending interrupts have the same group priority, the subpriority field determines
the order in which they are processed. If multiple pending interrupts have the same group
priority and subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority,
see
Descriptions of exception handling use the following terms:
•
•
•
•
•
•
Section 34.4.3.9 “System Handler Priority Registers”
Section 34.4.2.7 “Interrupt Priority
an upper field that defines the group priority
a lower field that defines a subpriority within the group.
Preemption
When the processor is executing an exception handler, an exception can preempt the
exception handler if its priority is higher than the priority of the exception being
handled. See
When one exception preempts another, the exceptions are called nested exceptions.
See
Return
This occurs when the exception handler is completed, and:
Section 34.4.3.6 “Application Interrupt and Reset Control
Section 34.3.3.7.1
All information provided in this document is subject to legal disclaimers.
Section 34.3.3.6
Rev. 2 — 19 August 2010
more information.
for more information about preemption by an interrupt.
Registers”.
Chapter 34: Appendix: Cortex-M3 user guide
Register”.
UM10360
© NXP B.V. 2010. All rights reserved.
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