LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 326

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 298: UART1 Line Control Register (U1LCR - address 0x4001 000C) bit description
UM10360
User manual
Bit
1:0
2
3
5:4
6
7
31:8
Symbol
Word Length
Select
Stop Bit Select
Parity Enable
Parity Select
Break Control
Divisor Latch
Access Bit (DLAB)
-
15.4.7 UART1 Line Control Register (U1LCR - 0x4001 000C)
15.4.8 UART1 Modem Control Register (U1MCR - 0x4001 0010)
UART receiver DMA
In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO
level becoming equal to or greater than trigger level, or if a character timeout occurs. See
the description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
UART transmitter DMA
In DMA mode, the transmitter DMA request is asserted on the event of the transmitter
FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA
controller.
The U1LCR determines the format of the data character that is to be transmitted or
received.
The U1MCR enables the modem loopback mode and controls the modem output signals.
Value Description
00
01
10
11
0
1
0
1
00
01
10
11
0
1
0
1
5-bit character length.
6-bit character length.
7-bit character length.
8-bit character length.
1 stop bit.
2 stop bits (1.5 if U1LCR[1:0]=00).
Disable parity generation and checking.
Enable parity generation and checking.
Odd parity. Number of 1s in the transmitted character and the attached
parity bit will be odd.
Even Parity. Number of 1s in the transmitted character and the attached
parity bit will be even.
Forced "1" stick parity.
Forced "0" stick parity.
Disable break transmission.
Enable break transmission. Output pin UART1 TXD is forced to logic 0
when U1LCR[6] is active high.
Disable access to Divisor Latches.
Enable access to Divisor Latches.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 15: LPC17xx UART1
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
0
0
0
0
0
0
NA
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