LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 441

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Table 384. I
I2EN I
cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I
addressed” slave state, and the STO bit is forced to “0”.
I2EN should not be used to temporarily release the I
I
STA is the START flag. Setting this bit causes the I
transmit a START condition or transmit a repeated START condition if it is already in
master mode.
When STA is 1 and the I
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition
after a delay of a half clock period of the internal clock generator. If the I
already in master mode and data has been transmitted or received, it transmits a repeated
START condition. STA may be set at any time, including when the I
addressed slave mode.
STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register. When STA is
0, no START condition or repeated START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I
interface is in master mode, and transmits a START condition thereafter. If the I
interface is in slave mode, an internal STOP condition is generated, but is not transmitted
on the bus.
STO is the STOP flag. Setting this bit causes the I
condition in master mode, or recover from an error condition in slave mode. When STO is
1 in master mode, a STOP condition is transmitted on the I
the STOP condition, STO is cleared automatically.
Bit
1:0
2
3
4
5
6
31:7
2
C-bus status is lost. The AA flag should be used instead.
2
Symbol Description
-
AA
SI
STO
STA
I2EN
-
C Interface Enable. When I2EN is 1, the I
I
0x400A 0000) bit description
2
2
C Control Set register (I2CONSET: I
C1, I2C1CONSET - address 0x4005 C000, I
All information provided in this document is subject to legal disclaimers.
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge flag.
I
STOP flag.
START flag.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
2
C interrupt flag.
C interface enable.
Rev. 2 — 19 August 2010
2
C interface is not already in master mode, it enters master mode,
2
C0, I2C0CONSET - address 0x4001 C000,
2
C interface is enabled. I2EN can be
2
2
C interface to transmit a STOP
C interface to enter master mode and
2
C-bus since, when I2EN is reset, the
2
C2, I2C2CONSET - address
Chapter 19: LPC17xx I2C0/1/2
2
C-bus. When the bus detects
2
2
C interface is in an
C block is in the “not
UM10360
© NXP B.V. 2010. All rights reserved.
2
C interface is
2
C-bus if it the
2
C
441 of 840
Reset
value
NA
0
0
0
0
0
NA
2
C