LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 734

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.3.1.3.7 CONTROL register
34.3.1.4 Exceptions and interrupts
Table 633.
[1]
The CONTROL register controls the stack used and the privilege level for software
execution when the processor is in Thread mode. See the register summary in
for its attributes. The bit assignments are shown in
Table 634.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active
stack pointer bit of the CONTROL register when in Handler mode. The exception entry
and return mechanisms update the CONTROL register.
In an OS environment, ARM recommends that threads running in Thread mode use the
process stack and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode
to the PSP, use the MSR instruction to set the Active stack pointer bit to 1, see
Section 34.2.10.7
Remark: When changing the stack pointer, software must use an ISB instruction
immediately after the MSR instruction. This ensures that instructions after the ISB execute
using the new stack pointer. See
The Cortex-M3 processor supports interrupts and system exceptions. The processor and
the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An
exception changes the normal flow of software control. The processor uses handler mode
to handle all exceptions except for reset. See
for more information.
Bits
[31:8]
[7:0]
Bits
[31:2]
[1]
[0]
This field is similar to the priority fields in the interrupt priority registers. The processor implements only
bits[7:M] of this field, bits[M-1:0] read as zero and ignore writes. The value of M depends on the specific
device. See
priority field values correspond to lower exception priorities.
Name
-
BASEPRI
Name
-
Active stack
pointer
Thread mode
privilege level
BASEPRI register bit assignments
CONTROL register bit assignments
Section 34.4.2.7 “Interrupt Priority Registers”
All information provided in this document is subject to legal disclaimers.
[1]
“MSR”.
Rev. 2 — 19 August 2010
Function
Reserved
Priority mask bits:
0x0000 = no effect
Nonzero = defines the base priority for exception processing.
The processor does not process any exception with a priority value
greater than or equal to BASEPRI.
Function
Reserved
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
Defines the Thread mode privilege level:
0 = privileged
1 = unprivileged.
Section 34.2.10.5 “ISB”
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.3.3.7.1
for more information. Remember that higher
Table
634.
and
Section 34.3.3.7.2
UM10360
© NXP B.V. 2010. All rights reserved.
Table 626
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