LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 56

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
4.7.3 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 -
Table 39.
0x400F C1A8 and PCLKSEL1 - 0x400F C1AC)
A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal
that will be supplied to the corresponding peripheral as specified in
Table
Remark: The peripheral clock for the RTC block is fixed at CCLK/8.
Table 40.
[1]
Bit
3:0
31:4
Bit
1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
17:16
19:18
21:20
23:22
25:24
27:26
29:28
31:30
PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.
42.
Symbol
USBSEL
-
Symbol
PCLK_WDT
PCLK_TIMER0
PCLK_TIMER1
PCLK_UART0
PCLK_UART1
-
PCLK_PWM1
PCLK_I2C0
PCLK_SPI
-
PCLK_SSP1
PCLK_DAC
PCLK_ADC
PCLK_CAN1
PCLK_CAN2
PCLK_ACF
USB Clock Configuration register (USBCLKCFG - address 0x400F C108) bit
description
Peripheral Clock Selection register 0 (PCLKSEL0 - address 0x400F C1A8) bit
description
All information provided in this document is subject to legal disclaimers.
Value Description
5
7
9
Rev. 2 — 19 August 2010
Selects the divide value for creating the USB clock from the
PLL0 output. Only the values shown below can produce even
number multiples of 48 MHz from the PLL0 output.
operation of the USB interface.
PLL0 output is divided by 6. PLL0 output must be 288 MHz.
PLL0 output is divided by 8. PLL0 output must be 384 MHz.
PLL0 output is divided by 10. PLL0 output must be 480 MHz.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Warning: Improper setting of this value will result in incorrect
Description
Peripheral clock selection for WDT.
Peripheral clock selection for TIMER0.
Peripheral clock selection for TIMER1.
Peripheral clock selection for UART0.
Peripheral clock selection for UART1.
Reserved.
Reserved.
Peripheral clock selection for SSP1.
Peripheral clock selection for DAC.
Peripheral clock selection for ADC.
Peripheral clock selection for CAN1.
Peripheral clock selection for CAN2.
Peripheral clock selection for PWM1.
Peripheral clock selection for I
Peripheral clock selection for SPI.
Peripheral clock selection for CAN acceptance filtering.
Chapter 4: LPC17xx Clocking and power control
2
C0.
[1]
[1]
Table
UM10360
© NXP B.V. 2010. All rights reserved.
40,
[1]
Table 41
56 of 840
Reset
value
0
NA
Reset
value
00
00
00
00
00
NA
00
00
00
NA
00
00
00
00
00
00
and